The present invention relates to a process via mismatch detecting device, and more particularly relates to a process via mismatch detecting device for detecting the misalignment of vias between various metal lines in a semiconductor process.
With the progress of semiconductor process technologies, the size of device is smaller and continuously reduced even to a sub-micro size or deep sub-micro size. Meanwhile, the size of IC is also decreased, so that the density of IC is increased continuously.
However, when the density of IC is rapidly increased, the multilevel interconnection process is needed in order to meet the increasing demand of interconnection after the minimization of transistors due to no sufficient area for making interconnections on the surface of a semiconductor substrate. Therefore, the design using two or more metal layers has gradually become a necessary method adopted by many IC fabrications. Furthermore, especially for the products with complicated functions, such as microprocessors and application chips, the design even with five or more metal layers has to be utilized to complete the connections among the devices inside the product.
In order to isolate each metal line, an insulator has to be placed between each of the metal layers. This insulator is generally called an intermetal dielectric (IMD) or interlevel dielectric (ILD). Please referring to FIG. 1, FIG. 1 is a cross-sectional diagram showing a conventional multilevel interconnection structure of IC, wherein a chip 10 has a transistor layer 80 and three metal layers. As shown in FIG. 1, the intermetal dielectric 50 is utilized between a metal layer 20 and a metal layer 30 and between the metal layer 30 and a metal layer 40, so as to isolate the metal layers with each other thereby avoiding short circuits. Moreover, by utilizing photolithography, vias 60 are defined at appropriate positions on the dielectric layer, and then plugs 70 are formed in the vias 60 with conductive material, such as tungsten, so that the current can flow freely among the metal layer 20, the metal layer 30 and the metal layer 40 through the plugs 70. By utilizing the design of multilevel interconnection, the transistors can be mutually interconnected so as to form a complete circuit on the chip 10.
In the earlier stage, since the IC design does not use many metal layers (mostly uses two or three metal layers), and the critical dimension thereof is broader, the metallization process of multilevel interconnection is relatively easily to be performed. However, while the multilevel interconnection is processed on a design with four metal layers, the surface of deposition layer is not smooth but rough, so that it is not easy to make the deposition layers aligned with each other. Particularly, when the vias interconnecting each of the metal layers are misaligned, the electrical properties of devices will be seriously affected, thus decreasing the reliability of product.
In view of the background of the invention described above, with the rapidly increasing density of IC, multi-metal layers are widely utilized in the multilevel interconnection process for the devices on a chip. However, because multiple deposition layers are not easy to be mutually aligned, and moreover, the electrical property of device is seriously affected especially when the vias interconnecting each of the metal layers are misaligned, thus, decreasing the product reliability.
It is the principal object of the present invention to provide a process via mismatch detecting device, and more particularly relates to a process via mismatch detecting device for detecting the misalignment of vias between various metal lines in a semiconductor process. While the vias between metal layers of chips are mismatched, according to the present invention, the vias on the detecting circuits of process via mismatch detecting device are mismatched as well. Therefore, by placing the vias of detecting circuits on proper locations, metal lines in various metal layers of detecting circuits will be short circuited by mismatched vias, and a voltage higher than the previous voltage before short-circuiting is generated and is regarded as a detected result of process via mismatch detecting device. Consequently, it is accurate and efficient to detect whether the vias between metal layers of chip are mismatched or not, and to detect the quantity and direction of the mismatch thereof, thereby appropriately adjusting and optimizing the process.
In accordance with the aforementioned purpose of the present invention, the present invention provides a process via mismatch detecting device comprising: a detecting circuit that comprises a first metal layer and a second metal layer, and the first metal layer comprises a first metal line and a second metal line, wherein the distance between the first metal line of the first metal layer and the second metal line of the first metal layer is a metal-line distance value, and one terminal of the first metal line of the first metal layer and one terminal of the second metal line of the first metal layer are electrically connected to a power source, and the second metal layer comprises a first metal line, a second metal line and a third metal line, wherein one terminal of the first metal line of the second metal layer is electrically connected to one terminal of a first resistor, and another terminal of the first resistor is electrically connected to a ground, and one terminal of the second metal line of the second metal layer is electrically connected to one terminal of a second resistor, and another terminal of the second resistor is electrically connected to the ground, and one terminal of the third metal line of the second metal layer is electrically connected to one terminal of a third resistor, and another terminal of the third resistor is electrically connected to the ground, and the first metal layer is located above the second metal layer and is placed orthogonally to the second metal layer, a dielectric layer located between the first metal layer and the second metal layer, wherein according to a predetermined via placement method, a first via is formed at a first predetermined location of the dielectric layer corresponding to the first metal line of the second metal layer, and a second via is formed at a second predetermined location of the dielectric layer corresponding to the second metal line of the second metal layer, and a third via is formed at a third predetermined location of the dielectric layer corresponding to the third metal line of the second metal layer; and a register having a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is electrically connected to another terminal of the first metal line of the second metal layer, and the second input terminal is electrically connected to another terminal of the second metal line of the second metal layer, and the third input terminal is electrically connected to another terminal of the third metal line of the second metal layer, and the output terminal outputs a detected result of the process via mismatch detecting device.
By utilizing the process via mismatch detecting device of the present invention, in order to accurately and efficiently detect the direction and quantity of mismatched via between metal layers in a chip, the vias of process via mismatch detecting device can be placed properly according to the quantity of metal layers in the chip and the required sensitivity of detecting via mismatch, so that proper adjustment can be made so as to increase the yield and to decrease the cost.